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Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX11008 returns to F/S mode. Use a repeated START
condition in place of a STOP condition to leave the bus
active and the mode unchanged. Figure 9 summarizes
the data bit transfer format for HS-mode communication.
Register Address/Data Bytes (Write Cycle)
A write cycle begins with the bus master issuing a
START condition followed by 7 address bits (see Figure
5 and Table 1) and a write bit (R/ W = 0). Once the
slave address is recognized and the write bit is
received, the MAX11008 (I 2 C slave) issues an ACK by
pulling SDA low for one clock cycle. The master then
sends the register address byte (command byte) to the
MASTER TO SLAVE
SLAVE TO MASTER
slave. The MSB of the register address byte is the
read/write bit for the destination register address of the
slave and must be set to 0 for a write cycle (see the
Register Address Map section). After receiving the
byte, the slave issues another acknowledge, pulling
SDA low for one clock cycle. The master then writes
two data bytes, receiving an ACK from the slave after
each byte is sent. The master ends the write cycle by
issuing a STOP condition. When operating in HS mode,
a STOP condition returns the bus into F/S mode (see
the HS I 2 C Mode section). Figure 10 shows a complete
write cycle.
F/S MODE
HS MODE
F/S MODE
S
MASTER CODE
N
Sr
SLAVE ADDRESS
R/W
A
DATA
A
P
Figure 9. Data-Transfer Format in HS Mode
MASTER TO SLAVE
SLAVE TO MASTER
4-BYTE WRITE CYCLE
N BYTES + ACK
Sr
HS MODE CONTINUES
SLAVE ADD
1
7
1 1
8
1
8
1
8
1
1
NUMBER OF BITS
S
SLAVE
ADDRESS
W A
REGISTER ADDRESS
BYTE
A
DATA BYTE
A
DATA BYTE
A P OR Sr
MSB DETERMINES
WHETHER TO READ OR WRITE TO
REGISTERS
Figure 10. Write Cycle
22
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